Cascaded Nth order (N&gt;2) feedforward sigma-delta modulators

ABSTRACT

The invention relates to a method for cascading two or more feedforward-type sigma-delta modulators, and a modulator system comprising at least two cascaded modulators (1, 2). According to the invention, each subsequent modulator (2) in the cascade quantizes the integrated signal estimate error (e) of the preceding modulator (1), the quantized error (e&#39;) is differentiated (3) and subtracted (6) from the quantized output signal (D&#34;) of the preceding modulator (1).

FIELD OF THE INVENTION

The invention relates to a method for cascading at least two sigma-deltamodulators, wherein an error of one modulator in the cascade isquantized by the next modulator in the cascade; the quantized error isdifferentiated; and the differentiated error is subtracted from thequantized output signal of said one modulator.

BACKGROUND OF THE INVENTION

In sigma-delta modulators (also known as delta-sigma modulators), thesignal is quantized by using only a small number of quantization levels(2-256, which corresponds to an A/D converter with a resolution of 1 to8 bits) at a high rate, usually 32-512 times the signal frequency. Theratio between the Nyquist sampling frequency (two times the usefulsignal band) and the used high sampling frequency is also calledoversampling ratio (M). A quantizer is a combination of an A/D and a D/Aconverter, in which an analog signal is converted by the A/D converterto a discrete digital value which is then immediately converted back toan analog voltage (value) by the D/A converter. A quantizing error(e_(k)) is the difference voltage (value) between the analog inputvoltage and the analog output voltage, and the quantizing noise is thespectrum (Q_(e)) of the quantizing error; in the case of the sigma-deltamodulator, the quantizing noise can be regarded as white noise. Theeffective value (E) of the white noise in a one-bit quantizer is (q/2)²with a one-bit, where q is the spacing between the quantization levels.A sigma-delta modulator configuration is such that the quantizer errortransfer function (NTF) to the output of the modulator is different fromthe signal transfer function (STF) from the input to the output of themodulator. The object is to provide a quantizing error transfer functionNTF with the highest possible attenuation within a desired passbandwhile the signal transfer function STF is as uniform as possible overthe whole passband. The STF and NTF are interdependent in a mannerdetermined by the used modulator structure. The order of the modulatoris the order of the NTF function, or the number of integrators in themodulator. By increasing the order of the modulator the amount ofquantizing noise in the passband can be decreased. Another way ofdecreasing the amount of quantizing noise in the passband is to increasethe oversampling ratio however, an increase in the oversampling ratioincreases the sampling frequency which in turn is limited by thecomponents used in the implementation. Therefore the only way to improvethe ratio (S/N_(q)) between the signal (S) and the quantizing noise(N_(q)) in the passband is to increase the order of the modulator or toimprove the NTF so that the attenuation in the passband is increasedwhile the order of the modulator and the oversampling ratio remainunchanged.

A conventional sigma-delta modulator with directly series-connectedintegrators is, however, difficult to implement due to the oscillationcaused by the feedback loop. Therefore higher-order sigma-deltamodulators have been formed by cascading two or more stable lower-ordersigma-delta modulators. The quantizing error of the first modulator inthe cascade connection (the difference between the input and outputsignals of the quantizer) is applied to the second modulator in thecascade, and the amount of quantizing noise over the signal band can bedecreased by suitably interconnecting the outputs of the blocks. A16-bit Oversampling A-to-D Conversion Using Triple-Integration NoiseShaping, IEEE Journal of Solid State Circuits, Vol. SC-22, No. 6,December 1987, p. 921 to 929, describes the cascading of first-ordersigma-delta modulators by the so-called MASH technique. FI Patent 80548describes the cascade connections of second-order multiple-feedbackmodulators.

SUMMARY OF THE INVENTION

The object of the present invention is to cascade two sigma-deltamodulator blocks to achieve a better SNRQ than what was possible in theprior art modulator system of the same order and with the sameoversampling ratio.

This is achieved by a method described in the introductory chapter,which according to the invention is characterized in that the error isthe error of the integrated signal estimate of said one modulator.

According to the invention, at least two nth-order sigma-delta modulatorblocks realized by a 1-bit quantizer are cascaded so that eachsubsequent modulator block quantizes 1-bit the signal estimate errorvoltage formed in the preceding modulator block, scaled by a scalar 1/Cto the operating range of the subsequent modulator. The 1-bit data ofthe subsequent modulator block is filtered by a digital filter having atransfer function which is the inverse of the transfer function of theintegrators of the first modulator block, and scaled by a scalar C, andthen subtracted from the 1-bit data of the first block, which data hasbeen delayed in an amount corresponding to the delay caused by thesubsequent modulator block. In this way the signal estimate error of thefirst block, quantized by the subsequent modulator block, can besubtracted from the output of the first block, and the accuracy of thesignal estimate is improved and the amount of quantizing noise on thesignal band is reduced. The obtained digital output is the output of a2*nth-order sigma-delta modulator. As distinct from the prior artcascading based on the re-quantization of the quantizing error, thecascading according to the invention based on the signal estimate errorensures that the signal transfer function of the entire modulator systemwill always be 1 irrespective of the coefficients (STF) of the usedmodulator block. The prior art re-quantization of the quantizing errorand the substraction of the error from the output of the first blocklinearizes the attenuation across the quantizer to a constant value (1),so that the signal transfer function is determined by the STF of thefirst modulator block.

The modulator blocks used in the invention are of the FF-type. Accordingto the invention the blocks are at least of the second order. The STF ofthe two blocks must be equal. As the first feedforward-type modulatorhas a single feedback for the quantized value (from the output to theinput), the signal estimate error is the voltage difference between thefeedbacked quantized signal (voltage) and the analog input voltage.However, the signal estimate error is integrated n times (n is thenumber of the integration stages) before it is applied to the subsequent(next) modulator. In addition, it is possible to subtract anappropriately weighted signal estimate (a 1-bit quantized voltage) fromthe signal estimate error.

In addition to the advantages of the higher-order modulator system andthe associated reduction in the amount of quantizing noise, the cascadeconnection can improve the signal-to-noise ratio (S/N+N_(q)) inpractical applications, because the required voltage scaling in theinput of the first modulator block is smaller than in the prior artcascaded modulators. The sensitivity of the modulator to the noise (N)of the circuit elements is at highest in the input stage, and so theperformance of nearly all modulators (with an accuracy higher than 16bits) is limited by the noise of the circuit elements of the firstintegrator. With less voltage scaling the physical noise (N) of thecircuit elements is relatively smaller.

The invention also relates to a sigma-delta modulator system comprisinga first sigma-delta modulator having at least two integration stages anda quantizing means for quantizing a primary signal; a means forproviding an error signal representing the quantizing noise of the firstmodulator; a second sigma-delta modulator means having at least twointegration stages and a quantizing means, for quantizing said errorsignal; a differentiation means having a transfer function substantiallyequal to the inverse function of the common transfer function of theintegration stages of the first modulator means, for differentiating theoutput signal of the second modulator means; a means for delaying aquantized primary signal in an amount corresponding to the delay of thesecond modulator means; and a means for subtracting the differentiatederror signal from the delayed quantized primary signal.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following the invention will be described in greater detail bymeans of illustrating embodiments with reference to the attacheddrawing, in which

FIG. 1 is a block diagram illustrating an nth-order sigma-deltamodulator system according to the invention;

FIG. 2 is a block diagram illustrating an nth-order feedforwardmodulator based on the connecting of an integrated signal estimate errorand suitable for use as a modulator block SD1 in FIG. 1; and

FIG. 3 is a block diagram illustrating an nth-order feedforwardmodulator suitable for use as a modulator block SD2 in FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

The present invention has a special range of applications in oversampledA/D converters. Oversampling generally means that the sampling frequencyFs is substantially higher than the lowest sampling frequency determinedby the Nyquist criterion, which is two times the highest frequency ofthe signal. The sampling frequency usually applied in oversampling is aninteger multiple of the Nyquist frequency, e.g. 32 or 64 (oversamplingratio).

However, the invention is applicable in any applications utilizing ahigher-order sigma-delta modulator.

FIG. 1 illustrates generally the cascading of two nth-order modulatorsSD1 and SD 2 according to the invention, but it is equally possible inthe invention to cascade several modulators in the same way. An inputsignal Din to be quantized is applied to a first modulator block SD1,which produces a quantized 1-bit output signal D', which is delayed in adelay block 5 by a delay z⁻ 1, and the delayed quantized signal D" isapplied to one input in a subtractor means 6. An integrated signalestimate error e of the modulator block SD1 is first scaled by acoefficient 1/C and then applied to the second modulator block SD2,which produces a quantized error signal e'. The signal e' isdifferentiated by a digital filter block 3 forming a differentiator, thetransfer function (1-z-⁻¹)^(n) of the filter block 3 being substantiallyequal to the inverse function of the common transfer function of theintegration stages of the modulator block SD1. The differentiated andquantized error signal e" is scaled by a coefficient C (the reciprocalof 1/C), and the scaled error signal e_(q) is applied to another inputin the subtractor means 6. As a result, the quantized error signal e_(q)is subtracted from the delayed quantized primary signal D", so that onlythe 2*nth-order quantizing noise of the modulator block SD2,differentiated n times, is retained in the output signal D' of thesystem.

In practice, it is preferable that the modulator blocks SD1 and SD2 areof the same order and have the same coefficient values. If the modulatorblocks SD1 and SD2 are not of the same order or have not the same numberof delays, the digital filter block 3 is difficult to implement as notonly the FIR differentiator but also the IIR part has to be realized byit. Therefore the cascading of modulator blocks SD1 and SD2 of unequalorder is a less interesting application. Accordingly, in the preferredembodiments of the invention, the order n of the differentiator realizedby the block 3 is equal to the order of the modulator blocks SD1 andSD2, and it eliminates the effect of the common transfer function of theinterations of the modulator block SD1 on the quantized error signal e'.The delay k of the delay block 5 has to be equal to the delay of themodulator block SD2, that is, the combined delay of its integrators. Inthe practical implementation the delay k consists of a number of clockperiods equal to the order n of the modulator block SD1, that is, n=k.The error signal is scaled by a coefficient 1/C, and so the voltage ofthe error signal will fall within the linear operating range of theblock SD2. Thereafter the digital output of the block SD2 is scaled bythe coefficient C so that the original signal level will be restored.The minimum value of the coefficient C is the ratio between themodulator coefficients b_(n) /b₁. The system, however, is operative evenat higher scaling coefficients C, although the SNRQ deteriorates withthe increasing coefficient.

Nth-order feedforward modulator structures will be described below asillustrating embodiments, which can be used as the blocks SD1 and SD2 inthe modulator system according to the invention.

FIG. 2 shows a feedforward modulator structure suitable for use as SD1,comprising a series connection of a subtractor 26 and n integrationstages 21-1 . . . 21-n in this order. The output voltage D₁ -D_(nN) Ofeach integration stage 21-1 . . . 21-n is connected through a respectivescaling means 24-1 . . . 24-n (each voltage being scaled by a respectivecoupling coefficient b1-bn) to a summing means 25, which combines thescaled voltages D₁ -D_(n) and applies the sum voltage Ds to a quantizer23. The quantizer 23 is a combination of an A/D and a D/A converter, inwhich the analog voltage Ds is converted by the A/D converter 23A to adiscrete digital value D', which is the output signal of the modulatorSD1 and which is immediately thereafter converted back to an analogvoltage Df (value) by the D/A converter 23B so as to establish anegative feedback from the output of the quantizer 23 to the input ofthe modulator SD1. For this purpose the quantized output signal D', thatis, the signal estimate, is converted by the D/A converter 23B into ananalog voltage Df and then applied to one input in the subtractor 26 tobe subtracted from the input voltage Din applied to the integrationstage 21-1. The difference voltage DO between the voltages Din and Df isthe signal estimate error.

The output voltage of the last integration stage 21-n, that is, theintegrated signal estimate error Dn may be the error voltage e appliedto the next modulator stage SD2 when scaled by the coefficient 1/C in ascaling means 28. In such a case the modulator does not comprise asubtractor 27 and a scaling means 29.

Alternatively, it is possible to use a subtractor 27 to one input ofwhich the output voltage of the integration stage 21-n is applied. Theoutput signal D' of the quantizer 23 is weighted (after having beenconverted into an analog voltage by the A/D converter 23B) by a scalingcoefficient x (where 0<×<4*b1/b2) in the scaling means 29 and furtherapplied to another input in the subtractor 27 (as shown by the brokenlines) so as to be subtracted from the voltage Dn, that is, from theintegrated signal estimate error to obtain their difference voltage e,which is preferably scaled in a scaling means 28 by a scalingcoefficient 1/C smaller than one (at least b_(n) /b₁) to decrease thesignal level to the operating range of the next modulator block SD2.

FIG. 3 shows a feedforward-type sigma-delta modulator structure suitablefor use as the modulator block SD2. In FIG. 3 the modulator comprises aseries connection of a subtractor 36 and n integration stages 31-1 . . .31-n in this order. The output voltage e₁ -e_(n) of each integrationstage 31-1 31-n is connected through a respective scaling means 34-1 . .. 34-n (each voltage being scaled by a respective coupling coefficientb1-bn) to a summing means 35. The output voltage of the last integrationstage 31-n is connected to the summing means 35 through a delay block 37connected in series with the scaling means 34-n. The delay z⁻(1-d2) ofthe delay block 37 is zero when the delay d2 of the integration stage31-n is one, and z⁻ 1 when the delay of the integration stage 31-n isunequal to 1 (d2=0). The summing means 35 combines the scaled voltagese₁ -e_(n) and applies the sum voltages to a quantizer 33. The quantizer33 is a combination of an A/D and a D/A converter, in which the analogvoltage es is converted by the A/D converter 33A into a discrete digitalvalue e', which is the output signal of the modulator SD2 and which isimmediately thereafter converted back to an analog voltage ef (value) bythe D/A converter 33B so as to establish a negative feedback from theoutput of the quantizer 33 to the input of the modulator SD2. For thispurpose the quantized output signal e', that is, the signal estimate isconverted into an analog voltage ef by the D/A converter 33B and appliedto one input in the subtractor 36 to be subtracted from the inputvoltage e of the integration stage 31-1. The output of the quantizer 33gives a quantized error signal e' which is applied to the differentiatorblock 3 shown in FIG. 1.

If the transmission zeros of the noise function of the modulator are tobe transferred from the zero frequency, the output voltage e_(n) of theintegration stage 31-n is feedbacked through a scaling means 39 having afeedback coefficient "a" to a subtractor 38 in the input of thepreceding integration stage 31-(n-1) to be subtracted from the inputvoltage of the integration stage. The subtractor 38 is, of course,omitted if the feedback is not provided. The transfer of thetransmission zeros from the zero frequency imposes a few additionalrequirements on the blocks SD1 and SD2. The integrators of the modulatorblocks SD1 and SD2 have to be delayed (generally a delay of at least twoclock periods in the outermost modulator feedback loop of the quantizedvalue, including the integrator delays; and a delay of one or two clockperiods for the feedback "a", including the integrator delays) in orderthat the block SD2 could produce a transmission zero in the noisefunction. If the feedback loop "a" comprises one delay, the transmissionzero will be positioned accurately on the unit circle of the z domain,and infinite attenuation will be obtained at this point. On thecontrary, if the feedback loop "a" comprises two delays, thetransmission zero will be positioned on a line which is tangent to theunit circle at a point (1, 0) so that an absolutely accuratetransmission zero is obtained at this point only; the zeros, however,are positioned so close to the circumference of the unit circle atoversampling ratios greater than 64 that there is no significantdifference in the amount of quantizing noise on the signal band ascompared with the accurate zero. If the order n of the modulator blocksSD1 and SD2 is higher than or equal to 3, the modulator block SD2 has tocomprise at least two delayed integration stages to achieve thetransmission zero.

The figures and the description related to them are only intended toillustrate the present invention. In its details, the modulator systemaccording to the invention may vary within the scope and spirit of theattached claims.

We claim:
 1. A method of cascading at least two feedforward sigma-deltamodulators, comprising the steps of:producing an integrated signalestimate of a primary signal, in a first feedforward sigma-deltamodulator; producing an integrated signal estimate error associated withsaid integrated signal estimate; quantizing the integrated signalestimate error, in a second feedforward sigma-delta modulator;differentiating the quantized error; and subtracting the differentiatedquantized error from the integrated signal estimate.
 2. A methodaccording to claim 1, wherein said error comprises an output signal of alast integration stage of the first feedforward sigma-delta modulator.3. A method according to claim 1 wherein said step of producing anintegrated signal estimate error is preceded by the steps of:scaling theintegrated signal estimate by a predetermined scaling coefficient; andsubtracting the scaled integrated signal estimate from the output signalof the last integration stage of the first feedforward sigma-deltamodulator.
 4. A feedforward sigma-delta modulator system comprising:afirst feedforward sigma-delta modulator which integrates and quantizes aprimary signal, said first feedforward sigma-delta modulatorincluding:at least two integration stages, each of said integrationstages having an associated output signal; quantizing means forquantizing said output signals of said integration stages to therebyproduce an integrated signal estimate of said primary signal; and means,responsive to said at least two integration stages, for providing anintegrated signal estimate error associated with said integrated signalestimate; a second feedforward sigma-delta modulator, operativelyconnected to said first feedforward sigma-delta modulator, whichintegrates and quantizes said integrated signal estimate error,including:at least two integration stages, each of said integrationstages producing an associated output signal; and quantizing means,responsive to said at least two integration stages, for quantizing saidoutput signals of said integration stages to thereby produce a quantizedintegrated signal estimate error; differentiating means, responsive tosaid second feedforward sigma-delta modulator, for differentiating thequantized integrated signal estimate error, said differentiating meanshaving a transfer function substantially equal to the inverse functionof a common transfer function of said at least two integration stages ofsaid first feedforward sigma-delta modulator; means, responsive to saidfirst feedforward sigma-delta modulator, for delaying said integratedsignal estimate by an amount corresponding to a delay associated withsaid second feedforward sigma-delta modulator; and means, responsive tosaid differentiating means and to said means for delaying saidintegrated signal estimate, for subtracting said differentiatedquantized integrated signal estimate error from said delayed integratedsignal estimate.
 5. A system according to claim 4:wherein said firstfeedforward sigma-delta modulator comprises:scaling means, responsive tosaid at least two integration stages, for scaling the output signals ofeach of said at least two integration stages; and summing means forsuffering the scaled output signals; wherein said quantizing meanscomprises means, responsive to said summing means, for quantizing thesummed scaled output signals; and wherein said first feedforwardsigma-delta modulator further comprises means, responsive to saidquantizing means, for negatively feeding back said quantized summedscaled output voltages to a first integration stage of said at least twointegration stages.
 6. A system according to claim 5, wherein saidintegrated signal estimate error comprises an output signal of a lastintegration stage of said at least two integration stages of said firstfeedforward sigma-delta modulator.
 7. A system according to claim 4wherein said first feedforward sigma-delta modulator comprises:secondscaling means responsive to said quantizing means of said firstfeedforward sigma-delta modulator, for scaling said integrated signalestimate; and subtracting means, responsive to said second scaling meansand to a last integration stage of said at least two integration stagesof said first feedforward sigma-delta modulator, for subtracting thescaled integrated signal estimate from the output signal of said lastintegration stage so as to provide said integrated signal estimateerror.
 8. A system according to claim 7, wherein said second feedforwardsigma-delta modulator comprises:means for negatively feeding back anoutput signal of at least one integration stage of said at least twointegration stages to a preceding integration stage of said at least twointegration stages; and wherein either said at least one integrationstage comprises means for delaying a signal input into said at least oneintegration stage or said preceding integration stage comprises meansfor delaying a signal input into said preceding integration stage.
 9. Asystem according to claim 7, further comprising:third scaling means,responsive to said first feedforward sigma-delta modulator, for scalingsaid integrated signal estimate error by a first scaling coefficientsmaller than one; and fourth scaling means, responsive to saiddifferentiating means, for scaling the quantized integrated signalestimate error by a second scaling coefficient substantially equal tothe reciprocal of said first scaling coefficient.